In order to protect integrated circuit devices (ICs) against damage due to electrostatic discharge, it is common to include either separate ESD protection devices for channeling high ESD currents to ground, or to create self protecting I/O cells in which the same device is used as a high current output driver as well as for ESD protection.
In 80% to 90% of CMOS applications, snapback NMOS structures are the protection solution used. These work adequately during pulsed ESD operation but experience difficulties at continuous excessive currents or very high currents. The limited energy dissipation capabilities of NMOS ESD protection clamps can be attributed to the extremely localized region for heat dissipation, which corresponds to approximately a 0.5 μm region near the gate-drain region. This becomes especially significant in the case of overvoltage cells as is discussed further below.
A typical N-MOS snapback device includes a gate defined by a poly layer, a drain in the form of an n+ region and silicide (cobalt or titanium silicide) and a source. A plot of the IV characteristics of such a snapback device is shown in FIG. 1 and indicated by reference numeral 100. As is shown by the curve 100, current increases virtually unchecked after triggering, and only tapers off at extreme currents due to increased resistance caused by heating. In order to avoid burn-out, it is important not only to limit the current, but also to avoid excessive local current densities. One prior art solution is to use a separation resistance in the form of an un-silicided portion (ballast) between the gate and the silicided drain. The IV characteristics of such an un-silicided portion are shown by curve 102 in FIG. 1, which shows a clear saturation current curve. Thus the ballast region acts as a saturation resistor. The combined effect of including a ballast region for the snapback NMOS device is shown by curve 104 which, in many instances, will provide a current limit as indicated.
However, the use of a ballasting region to act as a saturation resistor fails to adequately address the problems of soft gate leakage current degradation and hot carrier degradation (HCD) which occur not only under high current induced by an ESD pulse, but take place even before breakdown. (HCD is commonly ascribed to post-ESD stress caused by residual high voltage levels after triggering off. In the case of low leakage circuits, these voltage levels may be stored for a long time thereby causing long term overload, causing HCD of the gate oxide.) As mentioned above, NMOS devices are most vulnerable in the region along the edge of the gate oxide under high electric fields, currents, and lattice temperatures. This becomes especially critical in the case of double gate structures due to the larger drain-source spacing, as is discussed below.
NMOS snapback structures operate using strong avalanche multiplication of charge carriers to create conductivity modulation in the on-state. FIG. 2 shows a cross-sectional view that illustrates a conventional NMOS device. As shown in FIG. 2, NMOS 200 has gates 202, 204 formed on a p-type semiconductor material 206. Considering only the NMOS device defined by the gate 204, FIG. 2, further, shows a n-doped drain 210 and n-doped source 212 extending along the sides of the gate 204. In operation, when the voltage across the drain 210 and source 212 is positive but less than the trigger voltage, the voltage reverse biases the junction between the gate 204 and the n-type material of the drain 210 and source 212. The reverse-biased junction blocks charge carriers from flowing from drain to source in the absence of appropriate biasing of the gate. However, when the voltage across the drain and source is positive and equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication causing holes to be injected into the region beneath the gate 204. The increased number of holes increases the potential of the material beneath the gate 204 and eventually forward biases the junction between the gate and the source, causing the holes to be swept across the junction to be collected by the source 212. Similarly, electrons are swept across from the source to the drain. Some of the electrons injected into the region below the gate 204 recombine with holes and are lost while another part of the holes is lost through the substrate contact.
However, in the case of overvoltage cells, cascoded NMOS devices are commonly used to increase the operating voltage (for example to increase the operating voltage from 3.3 V to 5V.) Referring again to FIG. 2, if the structure were connected as a set of two cascoded devices with a dual gate, the gates 202 and 204 would serve as the gates of the cascoded structure, and the region 220 would act as the source, with the region 210 serving as the drain. However, in such a structure the drain-source spacing between the drain 210 and source 220 is considerably greater. For instance, in a 0.181 μm CMOS dual gate oxide process, the spacing will be approximately 1.2 μm. This causes more charge carriers to be lost instead of being swept across the junction. Consequently, a higher electric field is required for avalanche multiplication. The resultant higher electric field E, lattice temperature, and input ionization at the gate 204 exposes the region along the edge of the gate 204 to higher soft gate leakage current degradation and hot carrier degradation. The present invention proposes a new structure and method of reducing such degradation.